The Most Prevalent Terms Used in Next-Generation IC Packaging Methods

Semiconductor Review | Tuesday, January 21, 2025

Engineers must adapt to advanced IC packaging technology, a prominent feature of the "More than Moore" arena. As chip scaling becomes more challenging and expensive, engineers are placing multiple chips in advanced packages as an alternative. 

Fremont, CA: Design engineers and engineering managers must keep up with this crucial technology by understanding the basic terms in advanced IC packaging content. This will help them better understand the challenges and opportunities this technology presents.

Most common terms used in next-generation IC packaging techniques:

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2.5D packaging

2.5D packages use dies stacked on interposers, providing connectivity between chips. This incremental step from traditional 2D IC packaging technology enables finer lines and spaces. Developed by Xilinx in 2008, 2.5D packaging became famous for high bandwidth memory processor integration.

3D packaging

3D IC packages use logic dies stacked together, connecting using active interposers, unlike 2.5D IC packages. TSVs enable TSV stacking, and DRAM chips are shipped in 3D IC packages using the HBM technique.

Chiplets 

Chiplets are 3D IC packaging that enables heterogeneous integration of CMOS and non-CMOS devices. They are smaller SoCs that break a large SoC into more minor chips, improving yield and cost. Chiplets can be built on materials like silicon, glass, and laminate.

Fan-out 

Fan-out packages use epoxy mold compound to embed dies, reducing process flows and simplifying heterogeneous integration. This small form-factor package offered more I/Os than other types and was introduced by Apple in 2016 to integrate its 16-nm processor with mobile DRAM in one iPhone 7 package.

Fan-out wafer-level packaging (FOWLP)

FOWLP technique improves wafer-level packaging by embedding chips in epoxy molding compound, fabricating high-density redistribution layers and solder balls on wafer surfaces, and forming reconstituted wafers. Due to the substrate's larger size, this technique offers more external contact with silicon dies and relaxed die spacing.

Heterogeneous integration

Heterogeneous integration combines multiple components in a single package, improving functionality and operating characteristics in semiconductor devices.

High bandwidth memory (HBM)

HBM is a standardized stacked memory technology with TSVs, enhancing I/Os and bandwidth, primarily used in 2.5D packages for high-end servers and networking chips.

Interposer

Interposers, made of silicon and organic materials, are crucial in multi-chip dies and boards, facilitating electrical signals and enhancing 2.5D and 3D IC chip packages.

Redistribution layer (RDL)

Redistribution layers (RDLs) are copper metal connections connecting packages, reducing I/O pitch on large chipsets, and are essential in 2.5D and 3D packaging solutions for communication.

Through silicon via (TSV)

TSV is a crucial technology in 2.5D and 3D packaging solutions, enabling vertical interconnections through a die's silicon wafer. It is filled with copper and creates the shortest path between chips. Vias are etched, filled with conductive material, and thinned from the back side to expose the vias and metal.

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