The Optane technology pitch from Intel was that it was cheaper than DRAM but not significantly slower, while it was more expensive than NAND but significantly faster
FREMONT, CA: Intel has refuted claims that Optane cells cannot be read right away because they need to cool after being written, but it has declined to comment on claims that contractual limits have stifled Optane's adoption by third parties. After talking to those who were evaluating early 3D XPoint technology and who had met with both Micron and Intel Optane product managers and engineers, the suggested delayed read time cell cooling issue surfaced. Intel's 3D XPoint technology, based on phase-change memory cells, is known as Optane. Micron built the chips in its Lehi fab until the company pulled the plug on 3D XPoint sales, marketing, and manufacturing.
The Optane technology pitch from Intel was that it was cheaper than DRAM but not significantly slower, while it was more expensive than NAND but significantly faster. It has, however, struggled to find a market niche, and a new reason has been identified for this: the phase change memory cell inside it must be heated during the write operation and then cooled down. This means that information can't be read right away once it's been written.
To fix the problem, Intel had to add DRAM cache to an Optane DIMM/SSD, increasing the cost and complexity of the product and making the price/performance ratio more troublesome.
The statement that Optane 3D XPoint memory has to cool down after material has been written is inaccurate, Intel confirmed through a spokeswoman. Optane memory can be read instantly after it has been written, and no extra DRAM caching hardware is required.
According to Intel, the DRAM caching was necessary due to the speed differential between DRAM and Optane. The access latency of Optane 3D XPoint memory is intrinsically longer than DRAM, hence Optane is used in Memory Mode to alleviate this impact. A smaller set of DRAM DIMMs is used as a cache for the larger Optane memory area in this mode. At the solution level, the net performance is 90 to 100 percent of that of a DRAM-only implementation.