Insights on 2.5D & 3D Semiconductor Packaging Trends

Semiconductor Review | Wednesday, January 17, 2024

However, challenges exist in achieving the same level of interconnect feature reduction as Si-based packages, highlighting the need for more efficient and cost-effective materials in packaging.

Fremont, CA: As semiconductor packaging technologies advance from 1D PCBs to 3D hybrid bonding at the wafer level, we achieve single-digit micron meter interconnect pitches and high energy efficiency for more than 1000 GB/s bandwidth.

Four critical parameters shape advanced semiconductor packaging: power, performance, area, and cost:

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● Power: Improve power efficiency with innovative packaging.
● Performance: Expanding input/output (I/O) points by shortening interconnection pitches.
● Area: Chips used in high-performance computing require more oversized packaging, while chips used in 3D integration require a smaller z-form factor.
● Cost: Using alternatives and less expensive materials or improving production equipment efficiency to reduce packaging costs

2.5D

Silicon: The Silicon (Si)  interposer and Si bridge are two options for high-performance computing integration. The Si interposer uses an entire passive Si wafer but faces cost and manufacturing challenges. The localized Si bridge form is gaining prominence for fine features. Both are crucial for 2.5D packaging and are expected to increase use in scenarios where the Si interposer faces area limitations.

Organic: Organic-based packaging, using fan-out molding compounds instead of organic substrates, offers lower RC delay and cost-effective alternatives to silicon. However, challenges exist in achieving the same level of interconnect feature reduction as Si-based packages, highlighting the need for more efficient and cost-effective materials in packaging.

Glass: Glass, a material with advantageous properties like tunable Coefficient of Thermal Expansion (CTE), high dimensional stability, and a smooth surface, has gained interest as an interposer with routing features that rival silicon. However, its immature ecosystem and lack of large-volume mass production capability in the packaging industry hinder its growth. As the ecosystem matures and production capabilities improve, glass-based technologies in semiconductor packaging may continue to grow.

3D

Microbump: Microbump technology, based on the Thermal Compression Bonding (TCB) process, is widely used in various products. However, it faces challenges due to smaller solder ball sizes, increased Intermetallic Compounds (IMCs), and potential chip failure during reflow. Combined with higher resistivity than copper, these factors limit their use in high-performance component packaging.

Hybrid Bonding: Hybrid bonding is a technique that combines a dielectric material (SiO2) with embedded metal (Cu), resulting in permanent interconnections. It offers advantages like expanded I/O, increased bandwidth, enhanced 3D vertical stacking, improved power efficiency, and reduced parasitics and thermal resistance. However, it faces manufacturing complexities and higher costs.

 

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