Initial Steps in ASIC Design Flow

Initial Steps in ASIC Design Flow

Functional verification ensures the logical behavior and functionality of the circuit by simulation on a design entry level. This is the step where the verification team and design team come together to generate RTL code utilizing test-benches. This step is known as behavioral simulation.

FREMONT, CA: ASIC design flow is a well-developed process in silicon turnkey design. The ASIC design flow and its VLSI engineering steps can be determined depending on proven methodologies and best practices in ASIC chip designs.

Let us look at the initial steps in ASIC design flow:

Chip Specification

This is the step at which engineers establish features, functionalities (hardware/software interface), microarchitecture, specifications (Time, Power, Area, Speed) with ASIC design guidelines. Two different teams are involved at this step:

Verification team: Initiates test bench.

Design team: Creates RTL code.

Functional Verification

Functional verification ensures the logical behavior and functionality of the circuit by simulation on a design entry level. This is the step where the verification team and design team come together to generate RTL code utilizing test-benches. This step is known as behavioral simulation.

In this simulation, once the RTL code is generated in HDL, many code coverage metrics proposed for HDL. Here, engineers' goal is to recheck the correctness of the code utilizing test vectors and achieve it by 95 percent coverage test. This code coverage encompasses statement coverage, branch coverage, expression coverage, and toggle coverage.

The two types of simulation tools include:

Functional simulation tools: After the test-bench and design code, functional simulation checks logical behavior and its implementation on the basis of design entry.

Timing simulation tools: Verify that circuit design fulfills the timing requirements as well as ensure the design is free of circuit signal delays.

RTL Block Synthesis

Once the test-bench and RTL code are generated, the RTL team starts working on RTL description, translating the RTL code into a gate-level netlist utilizing a logical synthesis tool that meets required timing limitations. Following that, a synthesized database of the ASIC design is built into the system. When timing restrictions are met with the logic synthesis, the design advances to the design for testability (DFT) techniques.