Semiconductor packaging has evolved with integrated approaches, chipset design, insulation materials, epoxy composites, silver nanowires, Si-based composites, and advanced packaging technology for yield, reliability, and density.
FREMONT, CA: Modern packaging protects chips, improves thermal conductivity and reliability, and acts as a link between the chip's internal components and the external circuit. Recent manufacturing and materials science strides have significantly advanced semiconductor chip and electronics packaging.
Advanced Packaging for Modern Semiconductors
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Modern semiconductor packaging has made significant advancements, encompassing various integration approaches. One prevalent method is 2-D IC integration, which involves placing at least two chips on the same package substrate or fan-out redistribution layer (RDL) substrate. This approach is commonly seen in systems-in-package (SiP) and is widely used in consumer electronics like smartwatches and smartphones.
Another approach is 2.1-D IC integration, where delicate metal layers are fabricated directly on top of a build-up package substrate or high-density interconnect (HDI). In 2.5-D IC integration, chips are supported by a passive through-silicon via (TSV) interposer attached to a package substrate—examples include AMD's Radeon R9 Fury X GPU.
3-D integration involves stacking chips vertically, encompassing both 3-D IC packaging and 3-D IC integration. The critical difference lies in using TSVs in 3-D IC integration, which is absent in 3-D IC packaging.
Recent advancements include chipset design and heterogeneous integration packaging. For instance, Intel's field-programmable gate array (FPGA), similar to Xilinx/TSMC's Virtex, microprocessors like AMD's Extreme Performance Yield Computing (EPYC), and Intel's Lakefield, utilise chipset designs and heterogeneous integration packaging in high-volume manufacturing (HVM).
This innovative approach involves breaking System-on-Chip (SoC) into smaller chipsets from different design houses, foundries, wafer sizes, and companies. These chipsets, integrated using advanced packaging technology, create cohesive systems or subsystems with improved flexibility and performance.
Regarding electrical performance for insulation materials, there's a growing preference for materials with low dissipation factor (Df or loss tangent) and low dielectric constant (Dk or permittivity), especially in 5G applications. Dielectric films in multilayer substrates or Redistribution Layers (RDLs) act as interlayer adhesives, crucial for maintaining electronic component integrity and efficiency.
Novel Epoxy Composites Used for Semiconductor Packaging
In electronic packaging, nearly 90 per cent of Integrated Circuits (ICs) are housed within plastic electronic packaging utilising underfill materials. These materials typically consist of an epoxy matrix combined with high levels of silica and boast a low coefficient of thermal expansion (CTE).
However, commercially available epoxy-based underfill materials (EUMs) currently suffer from thermal conductivity of only 0.4 W/m⋅K. This inadequacy in thermal conductivity poses a challenge in meeting the escalating heat dissipation demands of next-generation high-power electronic devices.
Augmenting the thermal conductivity of epoxy composites is crucial, yet other factors govern their practical application as EUMs. Processing requirements and the operational demands of electronic devices must also be considered.
For example, liquid epoxy-based encapsulants must exhibit favourable fluidity at room temperature to efficiently fill spaces during capillary flow processes within completed Integrated Circuits (ICs).
Recent research underscores the ongoing efforts to optimise the thermal conductivity of EUMs while upholding essential factors like processability, electronic insulation, Coefficient of Thermal Expansion (CTE), and mechanical properties. However, these efforts still need to be completed.
Experiments conducted by researchers showcased that adding minute quantities (0.5 vol %) of silver nanowires (AgNWs) into EP/S-Al2O3 composites significantly boosted thermal conductivity without compromising processability. The rigid nanowires acted as bridges between the primary spherical particles, leading to a notable 106.5 per cent increase in thermal conductivity in the micro nano EP/AgNWs/S-Al2O3 composites with 40 vol per cent S-Al2O3 and 0.5 vol per cent AgNWs, compared to those devoid of AgNWs.
These findings underscore the potential of integrating multiscale fillers into epoxy composites to address the trade-off between thermal conductivity and processability effectively. This advancement makes such materials well-suited for deployment in high-power-density electronic devices.
Si-Based Reinforced Metal Matrix Composites for Electronics Packaging
Power chips used in high-tech equipment generate significant heat. However, the absence of micro-cooling technology results in elevated chip temperatures, which reduce lifespan, diminish capabilities, and lower reliability. Research to enhance chip cooling primarily centres on two approaches.
The first involves creating efficient micro-scale heat dissipation mechanisms, such as advanced heat sinks—the second concentrates on developing high-performance thermal management materials, optimising overall chip cooling.
Metal matrix composites (MMCs) are composed of a matrix metal with high thermal conductivity (TC) and reinforcing phases that show significant potential for development. SiC/Al composite materials possess exceptional properties, including high specific strength, specific modulus, elevated hardness, wear resistance, good thermal stability, and muscular fatigue strength.
Their manufacturability using conventional methods makes them highly promising for applications in electronic packaging materials.
Building on the success of SiC/Al electronic packaging materials, there is a growing interest in SiC-based composites featuring a Cu matrix (SiC/Cu). Leveraging microfabrication techniques, SiC/Cu composites are emerging as prime contenders for the next wave of electronic packaging materials.
These composites' high thermal conductivity (TC) and low coefficient of thermal expansion (CTE) make them particularly suitable for use in high-performance heat dissipation devices and electronic packaging applications.
The trend toward higher packaging density and thinner chips in chip manufacturing processes introduces increased sensitivity to stress, contaminants, and inconsistencies. Addressing these challenges requires developing new techniques, including low-cost, high-performance bonding and large-scale metrology with high precision.
These advancements are crucial to tackle manufacturing issues such as yield and reliability. Advanced packaging emerges as a promising solution to maximise the advantages of scaling down by exploring new architectures, reducing communication distances, and achieving higher packaging density.
To realise these goals, standardisation, adopting new techniques, co-design tools, and multi-scale multi-physics simulation techniques are essential for the sustainable development of advanced packaging technology.
