Chipmakers are steering towards radical changes in architectures, materials, and basic structures, resulting in more process steps involving complexities and rising costs across the board.
FREMONT, CA: Chipmakers are seeking fundamental changes in materials, architectures, and basic structures such as transistors and interconnect. FinFETs will lose steam at the leading edge after the 3nm (30 angstroms) node. Companies working at those nodes are searching for a gate-all-around transistor as the next transistor structure to achieve tighter control over gate leakage.
This approach will work for a couple more nodes and further with the rollout of worksheet FETs, an intermediary step. Yet companies using this technique use different names, conventions, technology mixes, and timelines, making it difficult to determine which has technology leadership at any specific moment.
Transistors are drastically evolving from bipolar devices to planar CMOS, to 3D finFETs, and now to nanosheet gates all around transistors. However, it will not change every generation or node where there is a need to introduce a new architecture because new transistors or architectures take more time. Investment in nanotechnology has a decade of history to have enough confidence to bring it to the 2nm node.
Due to varying costs, foundries will extend existing technologies as long as possible. There is a need for fine-tuning a plethora of process steps involving manufacturing equipment and new manufacturing processes developed by foundries. The critical metrics are time spent in manufacturing for each wafer, which contributes to cost and time to inefficient outcomes. Each step requires changes in everything from EDA tools–evaluated at each node and half-node for each foundry–to accurately insert different equipment into the manufacturing process. For complex chips, there will be multiple insertion points. This makes actual timelines difficult to pin down, and foundries may not move to the next technology node until they fail to improve using existing technologies.
Prominent process leaders at the forefront are deciding to shift to GAA FETs at 2nm. FnFETs at 3nm offer 18 per cent speed improvement using the same power, or 34 per cent power deduction at the same performance. However, with nanosheets, there will be 10 to 15 per cent speed enhancement, a 25 to 30 per cent power reduction, and a 1.1X density increase. The present design rules will be compatible at N2, allowing the reuse of IP.
Many companies are offering an advanced finFET at the current production node and are waiting for the next-generation node to be introduced in the coming years. The most advanced node, where they believe they can differentiate themselves, is currently in development with several customers. This helps them to better understand customers' needs and ways to satisfy their demands. Ensuring working with customers in the early stages to boost learning as much as possible while enabling business ecosystems and partners to serve customers is posing a huge challenge for organisations. The business environments are becoming more powerful and, over the years, with a lot of R&D inclusive.