Arasan ONFI 5.0 PHY enables data training, various power drives, and ZQ calibration, ensuring maximum operating speed and optimum signal integrity.
FREMONT, CA: Arasan Chip Systems, a leading provider of semiconductor IP for the Internet of Things (IoT), mobile, and automobile SoCs announced the immediate availability of their Total IP Solution for Nand Flash compliant to the Open Nand Flash Interface (ONFI) 5.0 Specification. Arasan's Total IP for ONFI v5.0 NAND Flash includes the Host controller IP, PHY IP, and software stack. The ONFI 5.0 Standard is 50% faster than the previous ONFI 4.2 standard. ONFI Test Chip is available on 12nm.
This NAND Flash Controller IP enables simple, dependable access to off-chip NAND flash devices at previously unheard-of speeds. The updated controller supports all ONFI Specification modes at all speeds. This includes the new NV-LPDDR4 mode, in addition to the legacy Single Data Rate (asynchronous), NV-DDR (synchronous), NV-DDR2, and NV-DDR3 double data rate modes.
It supports all timing modes for these interface modes, from the low 10MHz mode up to the brand new 1,200MHz (2.4GT/S) I/O speeds. The Arasan's ONFI 5.0 Host controller IP is the first in Arasan's ONFI host controller line to have a fully verified AXI interface. It comprises unique microcontroller architecture to ensure every ONFI data path is fully utilized in a multithreaded fashion. The Arasan's ONFI 5.0 Host controller IP also features a full Scatter gather Direct Memory Access (DMA) algorithm, capable of moving from the flash to system memory at speeds matching the speed of the flash interface.
Arasan's ONFI 5.0 PHY IP is designed to connect seamlessly with their ONFI 5.0 Host Controller IP. Arasan's ONFI 5.0 PHY has complete SDR, NV-DDR, NV-DDR2, NV-DDR3, and NV-LPDDR4 TX/RX functionality and supports all the speeds defined in the ONFI specification while remaining backward compatible with the prior versions of the ONFI specifications. In addition, Arasan ONFI 5.0 PHY enables data training, various power drives, and ZQ calibration, ensuring maximum operating speed and optimum signal integrity. The PHY uses a PLL / DLL combination to provide very flexible frequency access. The PHY also includes ESD protection on all of the various ONFI interface pins.