FuturePlus Systems
Experts in DDR Memory Testing and Validation

In the world of computing, double data rate (DDR) technology is a game-changer in enhancing data transfer speed in electronic devices. As the DDR standards laid down by Joint Electron Device Engineering Council (JEDEC) rapidly evolves, design and test engineers need to ensure their products comply with the latest standards to prevent memory issues that result in corruption of data for end users.

FuturePlus Systems is a leading developer of design verification and validation tools for DDR memory testing, and is making a difference in the computer design industry. For more than three decades, its innovative DDR memory test equipment and validation tools have ensured their clients’ computer memory buses comply with industry standard protocols.

FuturePlus is an active member in JEDEC task groups and committees. Its test equipment helps engineers assess DDR memory designs per the JEDEC specifications. It also stands apart with its DDR memory testing services for end users.

“We design advanced DDR memory testing equipment, and then use that equipment along with equipment from Keysight to offer memory testing services tailored to the needs of end users,” says Barbara Aichinger, Co-Founder and Vice President of New Business Development at FuturePlus Systems.

To aid computer design validation engineers, FuturePlus brings a wide portfolio of cutting-edge testing products that include logic analyzer probes for DDR3, DDR4, and DDR5 memory, MSO probes, DRAM BGA interposer probing, a DDR5 sideband bus protocol analyzer, and its proprietary DDR Detective® solution.

FuturePlus interacts with engineers from the time of establishing design specifications and guides them in deploying its equipment for testing, debugging, and validating DDR memory designs.

For the end users of DDR memory, like data centers, network device manufacturers, medical device companies, etc., there is a range of customized testing services that comprise memory analysis for high-performance applications, DIMM/SODIMM and memory channel validation testing, along with embedded memory testing. These services are offered through FuturePlus’s lab, where testing and auditing the systems and DDR memory subsystems sent by clients is done in a timely, efficient, and cost-effective manner.

In high-performance computer applications, a reduction of a single clock tick leads to significant performance improvement. DDR Detective®, FuturePlus’s tool for DDR memory compliance, validation, and performance analysis, helps users gain a comprehensive view of their critical applications’ performance, down to the memory bus level. Its performance counters record each clock edge transaction and provides users corresponding output data and charts. This gives users insights on modifying their memory controller codes to reduce clock ticks and improve application performance.

The DDR Detective®, along with logic analyzers and slot and BGA interposers, is also useful in memory channel validation testing. Using these tools, FuturePlus can find the customer’s DDR memory problem via its services.

In DIMM/SODIMM validation testing, FuturePlus tests client systems and their DIMMs/SODIMMs from multiple vendors and suggests possible improvements. Data centers looking to avoid row hammer events also benefit from the testing equipment’s built-in features for recognizing excessive activate commands that cause memory failures.

For embedded memory testing, FuturePlus deploys BGA interposers, flying lead sets, and mid-bus footprints to test “memory down” situations where the DRAM part is soldered directly to the PCB. The testing detects incorrect BIOS programming, potential signal integrity issues, and memory failures caused by manufacturing variations, and ensures the DRAM runs at JEDEC-specified speeds for high performance.

FuturePlus’s testing services help clients enhance their system performance, find bugs, and identify root cause of memory failures. Case in point, a client’s system had frequent memory failures overnight, hampering critical operations. FuturePlus discovered that the system’s BIOS was incorrectly instructing its memory controller to initiate power saving mode, turning off the clocks in its DDR3 memory. This information enabled the client to instruct their system vendors to turn on the clocks permanently, which solved the memory failure issue.

FuturePlus recently partnered with Granite River Labs, a renowned engineering services and testing automation solutions firm, to deliver more successes to engineers and end users. Combining its deep DDR memory expertise with Granite River Labs’ global footprint, FuturePlus is on a mission to take the computer design industry to new heights.