Easy-Logic Technology
Increasing the Efficiency of Performing Functional Engineering Change Order

Easy-Logic Technology was founded by three aspiring Ph.D. laurates who wanted to revolutionize the IC design process with a cutting-edge, fully automated engineering change order (ECO) solution.

Their remarkable journey started with the esteemed electronic design automation (EDA) contest hosted by the International Conference on Computer-Aided Design (ICCAD), where they secured three consecutive championship titles. Their solution consistently outshone established commercial tools, leaving a lasting impression on the industry. Inspired by their victories, the trio made the leap from academia to the commercial domain, making their EDA tool, EasylogicECO, available to all.

EasylogicECO presents a significant advantage to IC design teams by streamlining ECO tasks, encompassing from crucial register transfer level (RTL) changes to metal mask changes.

Traditionally, a significant challenge arises when critical bugs surface after the RTL stage. Rectifying these bugs necessitated revisiting multiple design stages of logic synthesis, design for testing, placement, and timing closure. This iterative process is one of the reasons for substantial delays to the design cycle.

EasylogicECO addresses these intricacies of functional ECO processes.

Leveraging patented algorithms specifically developed for logic rectification—similar to the patching processes used in software development—the tool offers a revolutionary approach to accelerate the patching process and substantially improve the success rate, allowing engineers to insert patches to fix bugs with ease. This circumvents unnecessary delays, providing an indispensable advantage to IC design teams. It significantly outperforms traditional ECO algorithms, showcasing a clear advantage in turnaround time and effectiveness.

“Fast turnaround time delivered by our easy-to-use EasylogicECO tools gives design teams the freedom to try various RTL coding methods and find the best ECO result,” says Sean Wei, Ph.D., co-founder, CEO, and CTO of Easy-Logic.

Based on the superior algorithm, EasyLogicECO offers a range of important patch optimization features, ensuring robust and optimal ECO results. In addition, EasyLogicECO caters to advanced design requirements, taking into account the impact of design changes on various aspects, seamlessly applies necessary adjustments for multi-bit registers, clock gating units, low-power units, and isolation cells, guaranteeing a smooth integration of ECO changes. This compatibility ensures strict adherence to the original design rules while effectively implementing circuit revisions.

EasylogicECO’s unique offerings also reformed the ECO landscape. One of these features is its standalone solution flow that allows a plug-and-play integration with user’s favorite tool flow to deliver the result seamlessly, reducing the learning curve to minimal yet sustain superior outcomes. Another aspect is the comprehensive Design-For-Test (DFT) support, accommodating specific testability requirements in the design. EasyLogicECO can also handle large-scale ECO changes, enabling modifications to hundreds of thousands of logic cells within a reasonable execution time. This capability extends beyond minor RTL changes, making it suitable for substantial logic function alterations.

With the advent of these emerging ECO technology, Easy-Logic has brought forth a promising approach to unlock substantial benefits in terms of accurate ECO results and quick turnaround times. This shift enhances design productivity as well as contributes to the development of more vigilant and competitive ASIC products.