Nirmalya Ghosh, CEO
Providing the best PPAL (Power, Performance, Area & Leakage—key metrics in SOC/ASIC design) is VLSI’s biggest challenge which is ably addressed by the combination of DXCorr’s highly optimized physical IPs, specific custom blocks, and their physical design teams.
In the quest to achieve a high degree of autonomy, DXCorr develops various in-house tools that push the boundaries of the chip design process. “By focusing on a deeper understanding of bottlenecks, systems and flow, the development of in-house tools allows DXCorr to cut out the fat and reduce both design cycle time and vendor dependency,” says Nirmalya Ghosh, the CEO of DXCorr. As an example, their in-house software expedites layout generation by allowing the code to do the heavy lifting such that minimal human intervention is required. The design team targets the best PPAL using proprietary algorithms with high-efficiency optimization analysis, allowing DXCorr to deliver the industry’s best custom physical IP solutions across various process nodes.
DXCorr’s IPs meet highly stringent automotive electromigration (EM) rules as provided by foundry as well as much lower IR Drop targets than traditional IP design by enabling associated solutions. Their judicious use of different modes of testing serves as a safety measure in their offerings for Automotive products.
The Advanced Portfolio
DXCorr’s portfolio covers physical IP blocks such as SRAMs, MRAMs (STT & SOT), Standard Cells & I/Os - accounting for most of the building blocks of SoC design.
Also available are specialized physical IPs-TCAMs, BCAMs, Multiport Register Files, Customizable Data-path, Custom PDK & PCELL for Mixed Signal IC design, and SoC hardening solutions from RTL2GDSII. Having mastered the hash engine in the FinFET process, DXCorr offers a full custom double- SHA256 ASIC IP for faster Bitcoin mining. “In the space of Deep Learning Accelerators (DLA), DXCorr’s Neural Compiler helps architects, designers and implementation teams build quickest time-to-market Deep Learning chips with predictable accuracy and performance targets,” mentions Nirmalya.
DXCorr provides very specialized standard cell solutions to meet unique power and performance requirements. After analyzing current performance issues, existing libraries are augmented with a set of “kicker” cells for significant performance and power improvement. The process is completely automated, thereby freeing up the engineer to work on other aspects of library development and optimization.
DXCorr develops High Performance and High Density SRAMs and MRAMs. Working on 7nm & 14nm FinFET, 22nm & 12nm FDSOI, 28nm & 40nm-lowpower process nodes, they resolve the conflict in concurrent read & concurrent write operations in two port SRAMs. Power-efficient, high-speed binary and ternary CAMs help clients stand out in a market that craves faster networks and more efficient processors.
By focusing on a deeper understanding of bottlenecks, systems and flow, the development of in-house tools allows DXCorr to cut out the fat and reduce both design cycle time and vendor dependency
Open-mindedness and Innovation
Rather than focusing on merely churning out serviceable designs, DXCorr emphasizes innovating at every step. There are no holy cows in DXCorr’s philosophy. Every idea can and must be challenged.
This is made possible due to a significant lack of hierarchy in the company’s work culture. The only thing that matters is the idea. Every employee is at liberty to question existing approaches and suggest improvements. The process of thought is unrestricted. Employees are encouraged to explore sub-domains other than their own to develop a holistic understanding of VLSI.
The impetus to this approach is provided by the leadership, who are found in the trenches with the typical employee, busy at work trying to optimize and improve. Such cerebral amalgamation allows ideas to flow thick and fast. Ideas nurtured this way will arise as the next big thing in chip design that will take DXCorr to greater heights of success and Industry leadership.