Testinsight: Testing And Designing With Closed Loop Systems

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Within any product development lifecycle, the design and test teams stand worlds apart, each with their own tools and technological languages. While designers see the world from what could be termed as a software simulation perspective, test engineers work with actual silicon chipsets that would ultimately be sold to consumers as finished products. This conundrum—which does not take into consideration continual feedback within the design-to-test cycle—has been popularised as the open-loop problem. Among the many forerunners attempting to solve this problem, a noteworthy solution comes from TestInsight, which complements the typical design-to-test processes by creating an ATE-aware test bench for accelerated, more efficient test programs.



TestInsight, with its agile approach to testing, assists engineers in reducing the production time, enhancing collaboration, and boosting production efficiencies by seamlessly inter-connecting simulation, ATPG and testing functions. With decades of experience in test engineering innovation, the firm’s technology (TDL™) stands out as the fastest tool to convert design vectors into ATE programs, facilitating rapid test development while eliminating the process of compiling code to a binary format. Virtual Tester™ (VT), a virtual ATE provided by the firm creates an ATE-aware Verilog model, which allows pre-silicon test program validation to prevent failures, thereby making production test debug time shorter and more predictable. The firm’s software solution empowers test, product, and DFT engineers in failure detection, creates efficient test processes that are 200x faster, and provides customers with high-quality test software.

TestInsight’s resolution to the open-loop syndrome eliminates the time-consuming nature and complexity of debugging failures reported by Automatic Test Equipment. For instance, the unidirectional passage of information from design to test phases in the absence of validation feedback places IC vendors at a serious risk, which could result in the malfunctioning of the device in the post-production stage simply for the lack of communication/ collaboration.
“Instead of brainstorming solutions and contributing to the resolution, such collaborations become a blame-storming situation where everyone holds each other responsible for the problem,” says Mr. Meir Gellis, manager of the company.



Complementing the design-to-test process with an ATE-aware test bench enables TestInsight to oversee the design environment and the conversion process, assuring that the tests are accurate and enabling clients to focus on some of the more mission-critical problems within the workflow.

Engineers that hear about this closed-loop approach for the first time could think that their test programs are already validated at the design stage. However, the tools used at this stage provide convenient abstractions for designers and as such, they might overlook some production-related considerations. Specifically, design environments often ignore ATE hardware limitations and are also unaware of pattern conversion to ATE format. These blind spots can be effectively handled when using VT.
  • So Rather Than Brainstorming Situations Where You Want Everyone To Be Contributing To The Solution, There Is The Blamestorming Situation Where Everyone Blames Each Other For The Problem


Acknowledging TestInsight’s reputation and excellence in engineering workflows, a major Fabless IC vendor approached the company with the requirement to shorten the duration between the development of the first silicon and customer samples; the client wanted to achieve this by fully automating their pattern conversion and verification process while reducing the time taken from a couple of months to a single week. Working directly with their DFT and test teams, TestInsight established a fully automated testing process allowing them to achieve this goal using TDL and Virtual Tester. Such a fast and effective process allowed the customer to shorten the time to market and avoid expensive mistakes.

Alongside such successful collaborations, TestInsight is the only select partner of both Teradyne and Advantest, making it the de-facto standard for design-to-test tools. These companies offer TestInsight’s software by default with their ATEs. Teradyne and Advantest control 90% of the SoC (System On a Chip) test market giving the firm endless opportunities to expand their market reach. “They share the enhancements and upgrades made in the machines with us and verify if our software fully supports and utilizes their systems, which are added advantages for all parties involved,” says Mr. Meir Gellis. These technological differentiators, notable collaborations, and a keen eye on newer trends and developments within the SoC space have collectively enabled TestInsight to stay at the top of the manufacturing value-chain, positioned as a key vendor to address varied requirements.

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Testinsight

Company
Testinsight

Headquarters
Ramat Gan, Israel

Management
Meir Gellis, Manager

Description
TestInsight empowers test, product and DFT engineers with innovative tools for creating efficient test programs.With its agile approach, the firm assists engineers to reduce the production test time and make itmore predictable by bridging simulation, ATPG and test while accelerating test program.